Recently, thin film photoelectric conversion elements formed by plasma CVD using a gas as a raw material have been attracting attention. Examples of such thin film photoelectric conversion elements include a silicon-based thin film photoelectric conversion element made of silicon-based thin films, a thin film photoelectric conversion element made of a CIS (CuInSe2) compound or a CIGS (Cu(In, Ga)Se2) compound, and the like. Development and product expansion of such thin film photoelectric conversion elements have been promoted. These photoelectric conversion elements have a major characteristic that they have the possibility of achieving both lower cost and higher performance, as they are formed by stacking a semiconductor layer or a metal electrode film on an inexpensive large-area substrate using a forming apparatus such as a plasma CVD apparatus or a sputtering apparatus, and then separating/connecting photoelectric conversion elements fabricated on the same substrate by laser patterning. In such a manufacturing process, however, an increase in the cost of a semiconductor layer manufacturing apparatus, which is a main apparatus for fabricating a device and represented by a plasma CVD apparatus, leads to an increase in the manufacturing cost of the photoelectric conversion elements, posing a barrier to widespread use thereof.
In view of such a problem, for example, Japanese Patent Laying-Open No. 2000-252495 (Patent Document 1) discloses a single chamber system successively forming a p-type semiconductor layer, an i-type crystalline silicon-based photoelectric conversion layer, and an n-type semiconductor layer in order inside the same plasma CVD forming chamber. With this system, the number of forming chambers can be reduced and the facility can be simplified, when compared with an in-line system and a multiple chamber system forming respective layers in separate forming chambers. Further, transfer between forming chambers is not required, reducing manufacturing time for a photoelectric conversion element.
Furthermore, Japanese Patent Laying-Open No, 2000-252495 (Patent Document 1) has a description “In order to prevent conductivity-type determining impurity atoms doped into a p-type semiconductor layer and an n-type semiconductor layer from being introduced into a semiconductor layer of a different type, it is necessary to sufficiently replace gas in the deposition chamber before forming respective semiconductor layers, for example by gas replacement for one hour using a purge gas such as hydrogen. Even when such a gas replacement process is performed, it has been impossible to attain good performance of an amorphous silicon solar cell. Therefore, the single chamber system has been used only for experimental purposes”. Accordingly, a method of forming a photoelectric conversion element having an amorphous silicon-based photoelectric conversion layer by the single chamber system has not been put to practical use.
Japanese Patent Laying-Open No. 2004-006537 (Patent Document 2) describes that auto-doping of boron into an i-type semiconductor layer can be suppressed by removing B2H6 gas and a substance caused by the B2H6 gas in a chamber, after formation of a p-type semiconductor layer, by (1) vacuum exhaust of the chamber, (2) gas replacement using H2 or SiH4 or both, and (3) plasma cleaning using an etching gas such as hydrogen gas.
However, there is a problem that, in the case of forming a semiconductor layer in a reaction chamber by plasma CVD, it is necessary to perform gas replacement for a long period of time in order to remove impurities that exist in the reaction chamber by gas replacement before forming the semiconductor layer and form a high quality semiconductor layer.
Further, as described in the above-mentioned techniques, in the method of forming a semiconductor layer of a thin film photoelectric conversion element by which a photoelectric conversion element having a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer is formed in the same reaction chamber by plasma CVD (i.e., single chamber system), conductivity-type determining impurity atoms doped into the p-type semiconductor layer and the n-type semiconductor layer are also introduced into a semiconductor layer of a different type, making it difficult to obtain a photoelectric conversion element with a good photoelectric conversion property. In particular, it is difficult and not operational at present to apply the single chamber system to an amorphous silicon-based thin film photoelectric conversion element.    Patent Document 1: Japanese Patent Laying-Open No. 2000-252495    Patent Document 2: Japanese Patent Laying-Open No. 2004-006537
The technology disclosed herein provides a semiconductor layer manufacturing method and a semiconductor layer manufacturing apparatus capable of forming a high quality semiconductor layer even by a single chamber system, with a shortened process time required for reducing a concentration of impurities that exist in a reaction chamber before forming the semiconductor layer, and provide a semiconductor device manufactured using such a method and apparatus.
The technology disclosed herein relates to a semiconductor layer manufacturing method of forming a semiconductor layer inside a reaction chamber capable of being hermetically sealed, including: an impurities removing step of removing impurities inside the reaction chamber using a replacement gas, and a semiconductor layer forming step of forming the semiconductor layer, the impurities removing step being a step in which a cycle composed of a replacement gas introducing step of introducing the replacement gas into the reaction chamber and an exhausting step of exhausting the replacement gas is repeated a plurality of times, the impurities removing step being performed at least before the semiconductor layer forming step.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, the semiconductor layer includes a plurality of layers having different conductivity types, and the semiconductor layer is formed inside the same reaction chamber.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, a pressure after introducing the replacement gas and a pressure after exhausting the replacement gas inside the reaction chamber are set beforehand; in the replacement gas introducing step, exhaust from the reaction chamber is stopped, and when a pressure inside the reaction chamber is increased to greater than or equal to the pressure after introducing the replacement gas, introduction of the replacement gas is stopped and the replacement gas introducing step is terminated; and, in the exhausting step, introduction of the replacement gas is stopped, and when the pressure inside the reaction chamber is reduced to less than or equal to the pressure after exhausting the replacement gas, the exhaust is stopped and the exhausting step is terminated.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, an allowable concentration [N] (unit: atoms/cm.sup.3) of impurity atoms inside the reaction chamber immediately before the semiconductor layer forming step is set beforehand, and a number n (unit: number of times) of the cycle satisfies an expression:[N]o×(M/m)n≦[N]
where [N]o (unit: atoms/cm3) represents a concentration of impurity atoms inside the reaction chamber before starting the cycle, m (unit: Pa) represents the pressure after introducing the replacement gas, and M (unit: Pa) represents the pressure after exhausting the replacement gas.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, a background pressure inside the reaction chamber immediately before the semiconductor layer forming step is greater than or equal to 0.1 Pa and less than or equal to 10000 Pa.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, the semiconductor layer is a semiconductor layer used in a photoelectric conversion element, and includes a p-type layer, an i-type layer, and an n-type layer; the semiconductor layer forming step includes a first conductive layer forming step of forming a first conductive layer made of a p-type layer or an n-type layer, a photoelectric conversion layer forming step of forming a photoelectric conversion layer made of an i-type layer on the first conductive layer, and a second conductive layer forming step of forming a second conductive layer made of a p-type layer or an n-type layer on the photoelectric conversion layer; and the first conductive layer and the second conductive layer are formed to have conductivity types different from each other.
Preferably, the semiconductor layer manufacturing method of the technology disclosed herein further includes a buffer layer forming step of forming a buffer layer made of an i-type layer between the first conductive layer forming step and the photoelectric conversion layer forming step.
Preferably, the semiconductor layer manufacturing method of the technology disclosed herein further includes the impurities removing step between the first conductive layer forming step and the buffer layer forming step.
Preferably, the semiconductor layer manufacturing method of the technology disclosed herein further includes the impurities removing step between the buffer layer forming step and the photoelectric conversion layer forming step.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, the buffer layer includes a plurality of layers, and the impurities removing step is further performed after each buffer layer is formed in the buffer layer forming step.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, the replacement gas is at least any of gases used to form an i-type layer.
Preferably, in the semiconductor layer manufacturing method of the technology disclosed herein, the semiconductor layer is made of a stack body of a plurality of pin semiconductors.
Further, the technology disclosed herein relates to a semiconductor layer manufacturing apparatus used for any of the semiconductor layer manufacturing methods described above, including a reaction chamber capable of being hermetically sealed for forming a semiconductor layer therein, a gas introducing portion for introducing a replacement gas into the reaction chamber, and a gas exhausting portion for exhausting the replacement gas from the reaction chamber.
Further, the technology disclosed herein relates to a semiconductor device, including a substrate, and a semiconductor layer and an electrode formed on the substrate, the semiconductor layer being manufactured using any of the semiconductor layer manufacturing methods described above or any of the semiconductor layer manufacturing apparatuses described above.
In the semiconductor layer manufacturing method and the semiconductor layer manufacturing apparatus of the technology disclosed herein, an operation of replacing a gas inside the reaction chamber is repeated a plurality of times before forming the semiconductor layer, and thus a concentration of impurity atoms that exist inside the reaction chamber can be reduced. Thereby, a concentration of impurities incorporated into the semiconductor layer can be reduced, and a high quality semiconductor layer can be manufactured even by a single chamber system. Further, in the technology disclosed herein, since process time required for reducing impurities can be shortened by performing the gas replacement operation a plurality of times, excellent mass productivity can also be obtained. Therefore, according to the technology disclosed herein, a high quality semiconductor device can be manufactured with good mass productivity.
The following reference numerals are included herein: 101: reaction chamber, 102: cathode electrode, 103: anode electrode, 105: impedance matching circuit, 106a, 106b: electric power introducing line, 107: substrate, 108: electric power supplying portion, 110: gas introducing portion, 116: gas exhausting portion, 117: pressure regulating valve, 118: gas 119: gas exhaust port, 200, 303, 305: thin film photoelectric conversion element, 201: first electrode, 202, 202a, 202b, 202c: first conductive layer, 203, 203a, 203b: buffer layer, 204, 204a, 204b, 204c photoelectric conversion layer, 205, 205a, 205b, 205c: second conductive layer, 206: second electrode, 207: semiconductor layer, 301a: first pin structure stack body, 301b, 301c: second pin structure stack body, 302, 304: double pin structure stack body, 401: glass substrate, 402: p-type amorphous silicon semiconductor layer, 403: i-type microcrystalline silicon semiconductor layer, 404: amorphous silicon layer.